PIC18CXX2
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Reset Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
TOSU
Applicable Devices
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
00-0 0000
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
242 442 252 452
242 442 252 452
242 442 252 452
---0 0000
0000 0000
0000 0000
---0 0000
0000 0000
0000 0000
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 000u
PRODH
PRODL
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
INTCON
INTCON2
INTCON3
INDF0
242 442 252 452
242 442 252 452
242 442 252 452
1111 -1-1
11-0 0-00
1111 -1-1
11-0 0-00
N/A
N/A
N/A
N/A
N/A
N/A
POSTINC0 242 442 252 452
POSTDEC0 242 442 252 452
N/A
N/A
N/A
PREINC0
PLUSW0
FSR0H
FSR0L
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
xxxx xxxx
N/A
---- 0000
uuuu uuuu
uuuu uuuu
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
WREG
INDF1
POSTINC1 242 442 252 452
POSTDEC1 242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
PREINC1
PLUSW1
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
DS39026B-page 26
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
