PIC18CXX2
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Reset Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Applicable Devices
FSR1H
FSR1L
BSR
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
---- 0000
xxxx xxxx
---- 0000
N/A
---- 0000
uuuu uuuu
---- 0000
N/A
---- uuuu
uuuu uuuu
---- uuuu
N/A
INDF2
POSTINC2 242 442 252 452
POSTDEC2 242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
PREINC2
PLUSW2
FSR2H
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
N/A
N/A
N/A
N/A
N/A
N/A
---- 0000
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
00-1 11q0
---- 0000
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
1111 1111
---- ---0
--00 0101
---- ---0
00-1 qquu
---- uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- ---u
--uu uuuu
---- ---u
uu-u qquu
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON(4, 6)
TMR1H
TMR1L
T1CON
TMR2
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
242 442 252 452
xxxx xxxx
xxxx xxxx
0-00 0000
xxxx xxxx
1111 1111
-000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
1111 1111
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1 242 442 252 452
SSPCON2 242 442 252 452
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 27
MICROCHIP [ MICROCHIP ]
