PIC18CXX2
RLNCF
Rotate Left f (no carry)
RRCF
Rotate Right f through Carry
[ label ] RRCF f,d,a
0 ≤ f ≤ 255
Syntax:
[ label ] RLNCF f,d,a
Syntax:
Operands:
Operands:
0 ≤ f ≤ 255
d
a
[0,1]
[0,1]
d
a
[0,1]
[0,1]
Operation:
(f<n>) → dest<n+1>,
(f<7>) → dest<0>
Operation:
(f<n>) → dest<n-1>,
(f<0>) → C,
(C) → dest<7>
Status Affected:
Encoding:
N,Z
Status Affected:
Encoding:
C,N,Z
0100
01da
ffff
ffff
0011
00da
ffff
ffff
Description:
The contents of register ’f’ are
rotated one bit to the left. If ’d’ is 0
Description:
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
the result is placed in WREG. If ’d’
is 1, the result is stored back in reg-
ister 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1,
then the bank will be selected as
per the BSR value (default).
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, then the
bank will be selected as per the
BSR value (default).
register f
Words:
Cycles:
1
1
register f
C
Words:
Cycles:
1
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Q Cycle Activity:
Q1
Decode
Read
register ’f’
Process
Data
Write to
destination
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write to
destination
RLNCF
REG, 1, 0
Example:
Before Instruction
RRCF
REG, 0, 0
Example:
REG
=
1010 1011
0101 0111
After Instruction
Before Instruction
REG
=
REG
C
=
=
1110 0110
0
After Instruction
REG
=
1110 0110
WREG
C
=
=
0111 0011
0
DS39026B-page 224
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
