PIC18CXX2
RETFIE
Return from Interrupt
[ label ] RETFIE s
s [0,1]
RETLW
Return Literal to WREG
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
k → WREG,
(TOS) → PC,
PCLATU, PCLATH are unchanged
(WS) → WREG,
Status Affected:
Encoding:
None
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
0000
1100
kkkk
kkkk
Description:
WREG is loaded with the eight bit
literal 'k'. The program counter is
loaded from the top of the stack
(the return address). The high
address latch (PCLATH) remains
unchanged.
Status Affected:
Encoding:
GIE/GIEH,PEIE/GIEL.
0000
0000
0001
000s
Description:
Return from Interrupt. Stack is
popped and Top of Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting the either the
high or low priority global inter-
rupt enable bit. If ’s’ = 1, the con-
tents of the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If ’s’ =
0, no update of these registers
occurs (default).
Words:
Cycles:
1
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal ’k’
Process
Data
pop PC from
stack, Write
to WREG
No
No
No
No
operation
operation
operation
operation
Words:
Cycles:
1
2
Example:
Q Cycle Activity:
Q1
Q2
Q3
Q4
CALL TABLE ; WREG contains table
;
;
offset value
WREG now has
table value
Decode
No
operation
No
operation
pop PC from
stack
;
Set GIEH or
GIEL
:
TABLE
No
operation
No
operation
No
operation
No
operation
ADDWF PCL
RETLW k0
RETLW k1
; WREG = offset
; Begin table
;
:
:
RETFIE
1
Example:
After Interrupt
RETLW kn
; End of table
PC
W
BSR
STATUS
=
=
=
=
TOS
WS
BSRS
Before Instruction
STATUSS
1
WREG
=
0x07
GIE/GIEH, PEIE/GIEL=
After Instruction
WREG
=
value of kn
DS39026B-page 222
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
