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PIC18C452-I/L 参数 Datasheet PDF下载

PIC18C452-I/L图片预览
型号: PIC18C452-I/L
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能微控制器,10位A / D [High-Performance Microcontrollers with 10-Bit A/D]
分类和应用: 微控制器
文件页数/大小: 296 页 / 4835 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18CXX2  
COMF  
Complement f  
Compare f with WREG, skip if f =  
WREG  
CPFSEQ  
Syntax:  
Operands:  
[ label ] COMF f,d,a  
0 f 255  
Syntax:  
[ label ] CPFSEQ f,a  
0 f 255  
d
a
[0,1]  
[0,1]  
Operands:  
a
[0,1]  
Operation:  
Operation:  
(f) dest  
(f) – (WREG),  
skip if (f) = (WREG)  
(unsigned comparison)  
Status Affected:  
Encoding:  
N,Z  
0001  
11da  
ffff  
ffff  
Status Affected:  
Encoding:  
None  
Description:  
The contents of register ’f’ are com-  
plemented. If ’d’ is 0 the result is  
0110  
001a  
ffff  
ffff  
stored in WREG. If ’d’ is 1 the result  
is stored back in register ’f’  
Description:  
Compares the contents of data  
memory location 'f' to the contents  
(default). If ’a’ is 0, the Access  
Bank will be selected, overriding  
the BSR value. If ’a’ = 1, then the  
bank will be selected as per the  
BSR value (default).  
of WREG by performing an  
unsigned subtraction.  
If 'f' = WREG, then the fetched  
instruction is discarded and an NOP  
is executed instead making this a  
two-cycle instruction. If ’a’ is 0, the  
Access Bank will be selected, over-  
riding the BSR value. If ’a’ = 1,  
then the bank will be selected as  
per the BSR value (default).  
Words:  
Cycles:  
1
1
Q Cycle Activity:  
Q1  
Q2  
Q3  
Q4  
Decode  
Read  
register ’f’  
Process  
Data  
Write to  
destination  
Words:  
Cycles:  
1
1(2)  
Note: 3 cycles if skip and followed  
by a 2-word instruction  
COMF  
REG, 0, 0  
Example:  
Before Instruction  
Q Cycle Activity:  
Q1  
REG  
=
0x13  
After Instruction  
Q2  
Q3  
Q4  
REG  
WREG  
=
=
0x13  
0xEC  
Decode  
Read  
register ’f’  
Process  
Data  
No  
operation  
If skip:  
Q1  
Q2  
Q3  
Q4  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
If skip and followed by 2-word instruction:  
Q1  
Q2  
Q3  
Q4  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
No  
No  
No  
No  
operation  
operation  
operation  
operation  
HERE  
CPFSEQ REG, 0  
Example:  
NEQUAL  
EQUAL  
:
:
Before Instruction  
PC Address  
=
HERE  
WREG  
REG  
=
=
?
?
After Instruction  
If REG  
PC  
=
=
WREG;  
Address (EQUAL)  
If REG  
PC  
=
WREG;  
Address (NEQUAL)  
DS39026B-page 208  
Preliminary  
7/99 Microchip Technology Inc.  
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