PIC18CXX2
Register 16-2: ADCON1 Register
R/W-0
ADFM
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7:6
bit 7
Unimplemented: Read as ’0’
ADFM: A/D Result format select.
1= Right justified. 6 Most Significant bits of ADRESH are read as ’0’.
0= Left justified. 6 Least Significant bits of ADRESL are read as ’0’.
bit 6
ADCS2: A/D Conversion Clock Select bit (shown in bold)
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock derived from the internal A/D RC oscillator)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock derived from the internal A/D RC oscillator)
Note: The ADCS1:ADCS0 bits are located in the ADCON0 register
Unimplemented: Read as ’0’
bit 5:4
bit 3:0
PCFG3:PCFG0: A/D Port Configuration Control bits
PCFG AN7 AN6 AN5 AN4 AN3
AN2
AN1 AN0 VREF+ VREF- C / R
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
D
D
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
VDD
AN3
VDD
AN3
VDD
AN3
—
VSS
VSS
VSS
VSS
VSS
VSS
—
8 / 0
7 / 1
5 / 0
4 / 1
3 / 0
2 / 1
0 / 0
6 / 2
6 / 0
5 / 1
4 / 2
3 / 2
2 / 2
1 / 0
1 / 2
VREF+
A
VREF+
A
VREF+
D
VREF+ VREF-
AN3
VDD
AN3
AN3
AN3
AN3
VDD
AN3
AN2
VSS
VSS
AN2
AN2
AN2
VSS
AN2
A
A
A
VREF+
VREF+ VREF-
VREF+ VREF-
VREF+ VREF-
D
D
VREF+ VREF-
A = Analog input D = Digital I/O
C/R = # of analog input channels / # of A/D voltage references
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: On any device reset, the port pins that are multiplexed with analog functions (ANx) are
forced to be an analog input.
DS39026B-page 168
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
