PIC18CXX2
FIGURE 15-5: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 15-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
POR,
BOR
Value on
all other
Resets
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON GIE/GIEH PEIE/ TMR0IE INT0IE RBIE TMR0IF INT0IF
GIEL
RBIF
0000 000x 0000 000u
PIR1
PSPIF(1)
PSPIE(1) ADIE
PSPIP(1) ADIP
ADIF
RCIF
RCIE
RCIP
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000
IPR1
RCSTA
SPEN
RX9
SREN CREN
—
FERR OERR RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
RCREG USART Receive Register
TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH TRMT TX9D
SPBRG
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Reception.
Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18C2X2 devices. Always maintain these bits
clear.
DS39026B-page 160
Preliminary
7/99 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
