PIC18CXX2
14.2.1.7 SLEEP OPERATION
In master mode all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode, and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
14.2.1.8 EFFECTS OF A RESET
A reset disables the MSSP module and terminates the
current transfer.
14.2.1.9 BUS MODE COMPATIBILITY
Table 14-1 shows the compatibility between the stan-
dard SPI modes and the states the the CKP and CKE
control bits.
TABLE 14-1: SPI BUS MODES
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
There is also a SMP bit which controls when the data is
sampled.
7/99 Microchip Technology Inc.
Preliminary
DS39026B-page 127
MICROCHIP [ MICROCHIP ]
