PIC18F6525/6621/8525/8621
6.2.4
16-BIT MODE TIMING
The presentation of control signals on the external
memory bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 6-4 through Figure 6-6.
FIGURE 6-4:
EXTERNAL MEMORY BUS TIMING FOR TBLRD (MICROPROCESSOR MODE)
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q4
Q1
Q4
Q2
Q4
Q3
Q4
Q4
Apparent Q
Actual Q
00h
0Ch
A<19:16>
3AABh
0E55h
9256h
AD<15:0>
CF33h
BA0
ALE
OE
WRH
‘1’
‘1’
WRL
CE
‘1’
‘0’
‘1’
‘0’
1 TCY Wait
Memory
Cycle
Opcode Fetch
MOVLW55h
Table Read
of 92h
from 007556h
from 199E67h
Instruction
Execution
TBLRDCycle 1
TBLRDCycle 2
FIGURE 6-5:
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Q1 Q2
Q3
Q4
Q1 Q2
Q3 Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
0Ch
A<19:16>
CF33h
9256h
AD<15:0>
CE
ALE
OE
Opcode Fetch
TBLRD*
from 000100h
Opcode Fetch
MOVLW55h
from 000102h
TBLRD92h
from 199E67h
Opcode Fetch
ADDLW55h
from 000104h
Memory
Cycle
Instruction
Execution
INST(PC – 2)
TBLRDCycle 1
TBLRDCycle 2
MOVLW
DS39612B-page 76
2005 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
