PIC18F6525/6621/8525/8621
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
IPR3
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
PIC18F6X2X PIC18F8X2X
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
xxxx xxxx
0000 xxxx
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
1111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
-111 1111(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
0000 uuuu
--uu uuuu
--uu uuuu
--uu uuuu
-u-u uuuu
-u-u uuuu(1)
-u-u uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
u-uu --uu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
MEMCON(9)
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5,6)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5,6)
PORTJ
PORTH
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for Reset value for specific condition.
5: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
7: If MCLR function is disabled, PORTG<5> is a read-only bit.
8: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
9: The MEMCON register is unimplemented and reads all ‘0’s when the device is in Microcontroller mode.
2005 Microchip Technology Inc.
DS39612B-page 35
MICROCHIP [ MICROCHIP ]
