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PIC18F8621-I/PT 参数 Datasheet PDF下载

PIC18F8621-I/PT图片预览
型号: PIC18F8621-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能, 64 KB的增强型闪存微控制器与A / D [64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路装置时钟
文件页数/大小: 396 页 / 6639 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F6525/6621/8525/8621  
REGISTER 18-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)  
R/W-0  
GCEN  
R/W-0  
R/W-0  
R/W-0  
R/W-0  
RCEN  
R/W-0  
PEN  
R/W-0  
RSEN  
R/W-0  
SEN  
ACKSTAT  
ACKDT  
ACKEN  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
GCEN: General Call Enable bit (Slave mode only)  
1= Enable interrupt when a general call address (0000h) is received in the SSPSR  
0= General call address disabled  
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)  
1= Acknowledge was not received from slave  
0= Acknowledge was received from slave  
ACKDT: Acknowledge Data bit (Master Receive mode only)  
1= Not Acknowledge  
0= Acknowledge  
Note:  
Value that will be transmitted when the user initiates an Acknowledge sequence at  
the end of a receive.  
bit 4  
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)  
1= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.  
Automatically cleared by hardware.  
0= Acknowledge sequence Idle  
bit 3  
bit 2  
RCEN: Receive Enable bit (Master mode only)  
1= Enables Receive mode for I2C  
0= Receive Idle  
PEN: Stop Condition Enable bit (Master mode only)  
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.  
0= Stop condition Idle  
bit 1  
bit 0  
RSEN: Repeated Start Condition Enable bit (Master mode only)  
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.  
0= Repeated Start condition Idle  
SEN: Start Condition Enable/Stretch Enable bit  
In Master mode:  
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.  
0= Start condition Idle  
In Slave mode:  
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)  
0= Clock stretching is disabled  
Note:  
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode,  
this bit may not be set (no spooling) and the SSPBUF may not be written (or writes  
to the SSPBUF are disabled).  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
2005 Microchip Technology Inc.  
DS39612B-page 185  
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