PIC18F6525/6621/8525/8621
18.3.8
SLEEP OPERATION
18.3.10 BUS MODE COMPATIBILITY
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
Table 18-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 18-1: SPI™ BUS MODES
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
Control Bits State
Standard SPI Mode
Terminology
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
0
1
1
1
0
1
0
18.3.9
EFFECTS OF A RESET
There is also a SMP bit which controls when the data is
sampled.
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 18-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIR1
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
SSPIF
SSPIE
SSPIP
TMR0IF
INT0IF
RBIF
0000 000x 0000 000u
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
TX1IF
TX1IE
TX1IP
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
1111 1111 1111 1111
(1)
(1)
PIE1
IPR1
TRISC
PORTC Data Direction Register
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3
MSSP Receive Buffer/Transmit Register
TRISF
TRISF2
TRISF1 TRISF0 1111 1111 1111 1111
xxxx xxxx uuuu uuuu
SSPBUF
SSPCON1
SSPSTAT
Legend:
WCOL
SMP
SSPOV
CKE
SSPEN
D/A
CKP
P
SSPM3
S
SSPM2
R/W
SSPM1 SSPM0 0000 0000 0000 0000
UA
BF
0000 0000 0000 0000
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI™ mode.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
2005 Microchip Technology Inc.
DS39612B-page 181