PIC18F6525/6621/8525/8621
18.3.3
ENABLING SPI I/O
18.3.4
TYPICAL CONNECTION
To enable the serial port, MSSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port
function, some must have their data direction bits (in
the TRIS register) appropriately programmed as
follows:
Figure 18-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their
programmed clock edge and latched on the opposite
edge of the clock. Both processors should be
programmed to the same Clock Polarity (CKP), then
both controllers would send and receive data at the
same time. Whether the data is meaningful (or dummy
data) depends on the application software. This leads
to three scenarios for data transmission:
• SDI is automatically controlled by the SPI module
• SDO must have TRISC<5> bit cleared
• Master sends data – Slave sends dummy data
• Master sends data – Slave sends data
• SCK (Master mode) must have TRISC<3> bit
cleared
• Master sends dummy data – Slave sends data
• SCK (Slave mode) must have TRISC<3> bit set
• SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 18-2:
SPI™ MASTER/SLAVE CONNECTION
SPI™ Master SSPM3:SSPM0 = 00xxb
SDO
SPI™ Slave SSPM3:SSPM0 = 010xb
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
2005 Microchip Technology Inc.
DS39612B-page 177
MICROCHIP [ MICROCHIP ]
