PIC18F6525/6621/8525/8621
FIGURE 10-22:
RJ4:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
RD TRISJ
CK
TRIS Latch
Control Out
System Bus
Control
External Enable
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-23:
RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTJ
RD LATJ
Data Bus
I/O pin(1)
Port
D
Q
0
1
Data
WR LATJ
or
PORTJ
CK
Data Latch
D
Q
WR TRISJ
CK
TRIS Latch
RD TRISJ
UB/LB Out
WM = 01
System Bus
Control
Drive System
Note 1: I/O pins have diode protection to VDD and VSS.
DS39612B-page 126
2005 Microchip Technology Inc.