PIC18F6525/6621/8525/8621
FIGURE 10-26:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
LATD
Port Data Latch when written; Port pins when read
LATD Data Output bits
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 ---- 0000 ----
0000 000x 0000 000u
TRISD
PORTE
LATE
PORTD Data Direction bits
Read PORTE pin/Write PORTE Data Latch
LATE Data Output bits
TRISE
PSPCON
INTCON
PIR1
PORTE Data Direction bits
(1)
IBF
OBF
IBOV
PSPMODE
INT0IE
TX1IF
—
—
—
—
GIE/GIEH PEIE/GIEL TMR0IE
RBIE
TMR0IF INT0IF
RBIF
(1)
PSPIF
PSPIE
PSPIP
ADIF
ADIE
ADIP
RC1IF
RC1IE
RC1IP
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
(1)
(1)
PIE1
TX1IE
IPR1
TX1IP
Legend:
x= unknown, u= unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
Note 1: Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
DS39612B-page 130
2005 Microchip Technology Inc.