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PIC18F8621-I/PT 参数 Datasheet PDF下载

PIC18F8621-I/PT图片预览
型号: PIC18F8621-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能, 64 KB的增强型闪存微控制器与A / D [64/80-Pin High-Performance, 64-Kbyte Enhanced Flash Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路装置时钟
文件页数/大小: 396 页 / 6639 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F6525/6621/8525/8621  
EXAMPLE 10-9:  
INITIALIZING PORTJ  
10.9 PORTJ, TRISJ and LATJ Registers  
CLRF  
PORTJ  
; Initialize PORTG by  
; clearing output  
; data latches  
Note:  
PORTJ is available only on PIC18F8525/  
8621 devices.  
CLRF  
LATJ  
; Alternate method  
; to clear output  
; data latches  
; Value used to  
; initialize data  
; direction  
; Set RJ3:RJ0 as inputs  
; RJ5:RJ4 as output  
; RJ7:RJ6 as inputs  
PORTJ is an 8-bit wide, bidirectional port. The corre-  
sponding data direction register is TRISJ. Setting a  
TRISJ bit (= 1) will make the corresponding PORTJ pin  
an input (i.e., put the corresponding output driver in a  
high-impedance mode). Clearing a TRISJ bit (= 0) will  
make the corresponding PORTJ pin an output (i.e., put  
the contents of the output latch on the selected pin).  
MOVLW  
MOVWF  
0xCF  
TRISJ  
The Data Latch register (LATJ) is also memory  
mapped. Read-modify-write operations on the LATJ  
register, read and write the latched output value for  
PORTJ.  
FIGURE 10-21:  
PORTJ BLOCK DIAGRAM  
IN I/O MODE  
PORTJ is multiplexed with the system bus as the  
external memory interface; I/O port functions are only  
available when the system bus is disabled. When  
operating as the external memory interface, PORTJ  
provides the control signal to external memory devices.  
The RJ5 pin is not multiplexed with any system bus  
functions.  
RD LATJ  
Data  
Bus  
D
Q
I/O pin(1)  
WR LATJ  
or  
PORTJ  
CK  
Data Latch  
When enabling peripheral functions, care should be  
taken in defining TRIS bits for each PORTJ pin. Some  
peripherals override the TRIS bit to make a pin an  
output, while other peripherals override the TRIS bit to  
make a pin an input. The user should refer to the corre-  
sponding peripheral section for the correct TRIS bit  
settings.  
D
Q
Schmitt  
Trigger  
Input  
WR TRISJ  
CK  
TRIS Latch  
Buffer  
RD TRISJ  
Note:  
On a Power-on Reset, these pins are  
configured as digital inputs.  
The pin override value is not loaded into the TRIS reg-  
ister. This allows read-modify-write of the TRIS register  
without concern due to peripheral overrides.  
Q
D
EN  
RD PORTJ  
Note 1: I/O pins have diode protection to VDD and VSS.  
2005 Microchip Technology Inc.  
DS39612B-page 125  
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