PIC18F6525/6621/8525/8621
FIGURE 10-11:
PORTE BLOCK DIAGRAM IN I/O MODE
Peripheral Out Select
Peripheral Data Out
VDD
P
0
1
(1)
I/O pin
RD LATE
Data Bus
D
Q
Q
WR LATE
or WR PORTE
CK
Data Latch
N
D
Q
Q
VSS
TRIS
WR TRISE
CK
TRIS OVERRIDE
Override
TRIS Latch
Pin Override
Peripheral
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
External Bus
RD TRISE
Schmitt
Trigger
Peripheral Enable
Q
D
EN
RD PORTE
Peripheral Data In
Note 1: I/O pins have diode protection to VDD and VSS.
FIGURE 10-12:
PORTE BLOCK DIAGRAM IN SYSTEM BUS MODE
Q
D
EN
EN
RD PORTE
RD LATE
Data Bus
(1)
I/O pin
Port
0
1
D
Q
Data
WR LATE
or PORTE
CK
Data Latch
D
Q
TTL
WR TRISE
CK
Input
Buffer
TRIS Latch
RD TRISE
Bus Enable
Data/TRIS Out
Drive Bus
System Bus
Control
Instruction Register
Instruction Read
Note 1: I/O pins have protection diodes to VDD and VSS.
2005 Microchip Technology Inc.
DS39612B-page 115
MICROCHIP [ MICROCHIP ]
