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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
To set up a Synchronous Slave Reception:  
20.5.2  
EUSART SYNCHRONOUS SLAVE  
RECEPTION  
1. Enable the synchronous master serial port by  
setting bits, SYNC and SPEN, and clearing bit,  
CSRC.  
The operation of the Synchronous Master and Slave  
modes is identical, except in the case of Sleep, or any  
Idle mode and bit SREN, which is a “don’t care” in  
Slave mode.  
2. If interrupts are desired, set enable bit, RCIE.  
3. If 9-bit reception is desired, set bit, RX9.  
4. To enable reception, set enable bit, CREN.  
If receive is enabled by setting the CREN bit prior to  
entering Sleep or any Idle mode, then a word may be  
received while in this Low-Power mode. Once the word  
is received, the RSR register will transfer the data to the  
RCREG register. If the RCIE enable bit is set, the inter-  
rupt generated will wake the chip from Low-Power  
mode. If the global interrupt is enabled, the program will  
branch to the interrupt vector.  
5. Flag bit, RCIF, will be set when reception is  
complete. An interrupt will be generated if  
enable bit, RCIE, was set.  
6. Read the RCSTA register to get the 9th bit (if  
enabled) and determine if any error occurred  
during reception.  
7. Read the 8-bit received data by reading the  
RCREG register.  
8. If any error occurred, clear the error by clearing  
bit, CREN.  
9. If using interrupts, ensure that the GIE and PEIE  
bits in the INTCON register (INTCON<7:6>) are  
set.  
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION  
Reset Values  
on Page:  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
INTCON  
PIR1  
GIE/GIEH PEIE/GIEL TMR0IE INT0IE  
RBIE  
TMR0IF INT0IF  
RBIF  
54  
57  
57  
57  
56  
56  
56  
56  
56  
56  
ADIF  
ADIE  
ADIP  
RX9  
RCIF  
RCIE  
RCIP  
SREN  
TXIF  
TXIE  
TXIP  
SSPIF CCP1IF TMR2IF TMR1IF  
SSPIE CCP1IE TMR2IE TMR1IE  
SSPIP CCP1IP TMR2IP TMR1IP  
PIE1  
IPR1  
RCSTA  
RCREG  
TXSTA  
BAUDCON  
SPBRGH  
SPBRG  
SPEN  
CREN ADDEN FERR  
OERR  
RX9D  
EUSART Receive Register  
CSRC  
TX9  
TXEN  
SYNC SENDB BRGH  
TRMT  
WUE  
TX9D  
RCIDL  
SCKP BRG16  
ABDEN  
EUSART Baud Rate Generator Register High Byte  
EUSART Baud Rate Generator Register Low Byte  
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.  
DS39616D-page 238  
2010 Microchip Technology Inc.  
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