欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/P的Datasheet PDF文件第202页浏览型号PIC18F4431-I/P的Datasheet PDF文件第203页浏览型号PIC18F4431-I/P的Datasheet PDF文件第204页浏览型号PIC18F4431-I/P的Datasheet PDF文件第205页浏览型号PIC18F4431-I/P的Datasheet PDF文件第207页浏览型号PIC18F4431-I/P的Datasheet PDF文件第208页浏览型号PIC18F4431-I/P的Datasheet PDF文件第209页浏览型号PIC18F4431-I/P的Datasheet PDF文件第210页  
PIC18F2331/2431/4331/4431  
REGISTER 19-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER  
R/W-0  
SMP  
R/W-0  
CKE  
R-0  
D/A  
R-0  
P
R-0  
S
R-0  
R-0  
UA  
R-0  
BF  
R/W  
bit 7  
bit 0  
Legend:  
R = Readable bit  
-n = Value at POR  
W = Writable bit  
‘1’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
‘0’ = Bit is cleared x = Bit is unknown  
bit 7  
SMP: Sample bit  
SPI Master mode:  
1= Input data sampled at end of data output time  
0= Input data sampled at middle of data output time  
SPI Slave mode:  
SMP must be cleared when SPI is used in Slave mode.  
bit 6  
CKE: SPI Clock Edge Select bit (Figure 19-2, Figure 19-3 and Figure 19-4)  
SPI mode, CKP = 0:  
1= Data transmitted on rising edge of SCK  
0= Data transmitted on falling edge of SCK  
SPI mode, CKP = 1:  
1= Data transmitted on falling edge of SCK  
0= Data transmitted on rising edge of SCK  
I2C™ mode:  
This bit must be maintained clear.  
bit 5  
bit 4  
D/A: Data/Address bit (I2C mode only)  
1= Indicates that the last byte received or transmitted was data  
0= Indicates that the last byte received or transmitted was address  
P: Stop bit (I2C mode only)  
This bit is cleared when the SSP module is disabled or when the Start bit is detected last; SSPEN is  
cleared.  
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)  
0= Stop bit was not detected last  
bit 3  
bit 2  
S: Start bit (I2C mode only)  
This bit is cleared when the SSP module is disabled or when the Stop bit is detected last; SSPEN is  
cleared.  
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)  
0= Start bit was not detected last  
R/W: Read/Write Information bit (I2C mode only)  
This bit holds the R/W bit information following the last address match. This bit is only valid from the  
address match to the next Start bit, Stop bit or ACK bit.  
1= Read  
0= Write  
bit 1  
bit 0  
UA: Update Address bit (10-Bit I2C mode only)  
1= Indicates that the user needs to update the address in the SSPADD register  
0= Address does not need to be updated  
BF: Buffer Full Status bit  
Receive (SPI and I2C modes):  
1= Receive complete, SSPBUF is full  
0= Receive not complete, SSPBUF is empty  
Transmit (I2C mode only):  
1= Transmit in progress, SSPBUF is full  
0= Transmit complete, SSPBUF is empty  
DS39616D-page 206  
2010 Microchip Technology Inc.  
 复制成功!