PIC18F2331/2431/4331/4431
FIGURE 18-1:
POWER CONTROL PWM MODULE BLOCK DIAGRAM
Internal Data Bus
8
PWMCON0
PWM Enable and Mode
8
8
8
8
PWMCON1
DTCON
Dead-Time Control
Fault Pin Control
FLTCONFIG
PWM Manual Control
OVDCON<D/S>
(1)
PWM Generator #3
PDC3 Buffer
8
PDC3
Channel 3
Dead-Time Generator
and Override Logic
(2)
(2)
Comparator
PWM7
PWM6
(2)
8
PWM
Generator 2
Channel 2
Dead-Time Generator
and Override Logic
PWM5
PWM4
PTMR
Comparator
PTPER
Output
Driver
Block
PWM
Generator 1
Channel 1
Dead-Time Generator
and Override Logic
PWM3
PWM2
PWM
Generator 0
Channel 0
Dead-Time Generator
and Override Logic
PWM1
PWM0
8
8
PTPER Buffer
FLTA
PTCON
(2)
FLTB
Special Event
Postscaler
Comparator
Special Event Trigger
SEVTDIR
PTDIR
8
SEVTCMP
Note 1: Only PWM Generator 3 is shown in detail. The other generators are identical; their details are omitted for clarity.
2: PWM Generator 3 and its logic, PWM Channels 6 and 7, and FLTB and its associated logic are not implemented on
PIC18F2331/2431 devices.
DS39616D-page 174
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
