欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC18F4431-I/P的Datasheet PDF文件第172页浏览型号PIC18F4431-I/P的Datasheet PDF文件第173页浏览型号PIC18F4431-I/P的Datasheet PDF文件第174页浏览型号PIC18F4431-I/P的Datasheet PDF文件第175页浏览型号PIC18F4431-I/P的Datasheet PDF文件第177页浏览型号PIC18F4431-I/P的Datasheet PDF文件第178页浏览型号PIC18F4431-I/P的Datasheet PDF文件第179页浏览型号PIC18F4431-I/P的Datasheet PDF文件第180页  
PIC18F2331/2431/4331/4431  
18.1 Control Registers  
18.2 Module Functionality  
The operation of the PWM module is controlled by a  
total of 22 registers. Eight of these are used to  
configure the features of the module:  
The PWM module supports several modes of operation  
that are beneficial for specific power and motor control  
applications. Each mode of operation is described in  
subsequent sections.  
• PWM Timer Control Register 0 (PTCON0)  
• PWM Timer Control Register 1 (PTCON1)  
• PWM Control Register 0 (PWMCON0)  
• PWM Control Register 1 (PWMCON1)  
• Dead-Time Control Register (DTCON)  
• Output Override Control Register (OVDCOND)  
• Output State Register (OVDCONS)  
The PWM module is composed of several functional  
blocks. The operation of each is explained separately  
in relation to the several modes of operation:  
• PWM Time Base  
• PWM Time Base Interrupts  
• PWM Period  
• PWM Duty Cycle  
• Fault Configuration Register (FLTCONFIG)  
• Dead-Time Generators  
• PWM Output Overrides  
• PWM Fault Inputs  
There are also 14 registers that are configured as  
seven register pairs of 16 bits. These are used for the  
configuration values of specific features. They are:  
• PWM Special Event Trigger  
• PWM Time Base Registers (PTMRH and PTMRL)  
• PWM Time Base Period Registers (PTPERH and  
PTPERL)  
18.3 PWM Time Base  
• PWM Special Event Trigger Compare Registers  
(SEVTCMPH and SEVTCMPL)  
The PWM time base is provided by a 12-bit timer with  
prescaler and postscaler functions. A simplified block  
diagram of the PWM time base is shown in Figure 18-4.  
The PWM time base is configured through the  
PTCON0 and PTCON1 registers. The time base is  
enabled or disabled by respectively setting or clearing  
the PTEN bit in the PTCON1 register.  
• PWM Duty Cycle #0 Registers  
(PDC0H and PDC0L)  
• PWM Duty Cycle #1 Registers  
(PDC1H and PDC1L)  
• PWM Duty Cycle #2 Registers  
(PDC2H and PDC2L)  
Note:  
The PTMR register pair (PTMRL:PTMRH)  
is not cleared when the PTEN bit is  
cleared in software.  
• PWM Duty Cycle #3 Registers  
(PDC3H and PDC3L)  
All of these register pairs are double-buffered.  
DS39616D-page 176  
2010 Microchip Technology Inc.