PIC18F2331/2431/4331/4431
TABLE 17-8: REGISTERS ASSOCIATED WITH THE MOTION FEEDBACK MODULE
ResetValues
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page:
INTCON
IPR3
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
IC1IP
IC1IE
IC1IF
RBIF
54
56
56
56
57
57
57
57
57
58
—
—
—
—
—
—
—
—
—
PTIP IC3DRIP IC2QEIP
PTIE IC3DRIE IC2QEIE
PTIF IC3DRIF IC2QEIF
TMR5IP
TMR5IE
TMR5IF
PIE3
PIR3
TMR5H
TMR5L
PR5H
PR5L
Timer5 Register High Byte
Timer5 Register Low Byte
Timer5 Period Register High Byte
Timer5 Period Register Low Byte
T5CON
T5SEN
RESEN
T5MOD T5PS1 T5PS0 T5SYNC TMR5CS TMR5ON
CAP1BUFH/ Capture 1 Register High Byte/Velocity Register High Byte(1)
VELRH
CAP1BUFL/ Capture 1 Register Low Byte/Velocity Register Low Byte(1)
VELRL
CAP2BUFH/ Capture 2 Register High Byte/QEI Position Counter Register High Byte(1)
58
58
58
58
58
POSCNTH
CAP2BUFL/ Capture 2 Register Low Byte/QEI Position Counter Register Low Byte(1)
POSCNTL
CAP3BUFH/ Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte(1)
MAXCNTH
CAP3BUFL/ Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte(1)
MAXCNTL
CAP1CON
CAP2CON
CAP3CON
DFLTCON
QEICON
—
—
CAP1REN
CAP2REN
CAP3REN
FLT4EN
—
—
—
—
—
—
CAP1M3 CAP1M2 CAP1M1 CAP1M0
CAP2M3 CAP2M2 CAP2M1 CAP2M0
CAP3M3 CAP3M2 CAP3M1 CAP3M0
59
59
59
59
56
—
—
FLT3EN FLT2EN FLT1EN FLTCK2 FLTCK1 FLTCK0
QEIM0 PDEC1 PDEC0
VELM
QERR UP/DOWN QEIM2 QEIM1
Legend: — = unimplemented. Shaded cells are not used by the Motion Feedback Module.
Note 1: Register name and function determined by which submodule is selected (IC/QEI, respectively). See
Section 17.1.10 “Other Operating Modes” for more information.
2010 Microchip Technology Inc.
DS39616D-page 171
MICROCHIP [ MICROCHIP ]
