PIC18F2331/2431/4331/4431
FIGURE 18-2:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE
VDD
Dead-Band
Generator
PWM1
Duty Cycle Comparator
HPOL
LPOL
PWM Duty Cycle Register
PWM0
Fault Override Values
Channel Override Values
Fault A Pin
Fault B Pin
Fault Pin Assignment
Logic
Note:
In Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active.
The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd channel
is driven to its active state.
FIGURE 18-3:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE
VDD
PWM Duty Cycle Register
PWM1
Duty Cycle Comparator
HPOL
VDD
PWM0
Fault Override Values
LPOL
Channel Override Values
Fault A Pin
Fault B Pin
Fault Pin Assignment
Logic
This module contains four duty cycle generators,
numbered 0 through 3. The module has eight PWM
output pins, numbered 0 through 7. The eight PWM
outputs are grouped into output pairs of even and odd
numbered outputs. In Complementary modes, the even
PWM pins must always be the complement of the
corresponding odd PWM pin. For example, PWM0 will
be the complement of PWM1, PWM2 will be the
complement of PWM3 and so on. The dead-time
generator inserts an OFF period called “dead time”
between the going OFF of one pin to the going ON of
the complementary pin of the paired pins. This is to
prevent damage to the power switching devices that
will be connected to the PWM output pins.
The time base for the PWM module is provided by its
own 12-bit timer, which also incorporates selectable
prescaler and postscaler options.
2010 Microchip Technology Inc.
DS39616D-page 175
MICROCHIP [ MICROCHIP ]
