PIC18F2331/2431/4331/4431
17.2.6
VELOCITY MEASUREMENT
17.2.6.1
Velocity Event Timing
The velocity pulse generator, in conjunction with the
IC1 and the synchronous TMR5 (in synchronous
operation), provides a method for high accuracy speed
measurements at both low and high mechanical motor
speeds. The Velocity mode is enabled when the VELM
bit is cleared (= 0) and QEI is set to one of its operating
modes (see Table 17-6).
The event pulses are reduced by a fixed ratio by the
velocity pulse divider. The divider is useful for
high-speed measurements where the velocity events
happen frequently. By producing a single output pulse
for a given number of input event pulses, the counter
can track larger pulse counts (i.e., distance travelled)
for a given time interval. Time is measured by utilizing
the TMR5 time base.
To optimize register space, the Input Capture
Channel 1 (IC1) is used to capture TMR5 counter
values. Input Capture Buffer register, CAP1BUF, is
redefined in Velocity Measurement mode, VELM = 0,
as the Velocity Register Buffer (VELRH, VELRL).
Each velocity pulse serves as a capture pulse. With the
TMR5 in Synchronous Timer mode, the value of TMR5
is captured on every output pulse of the postscaler. The
counter is subsequently reset to ‘0’. TMR5 is reset
upon a capture event.
TABLE 17-6: VELOCITY PULSES
Figure 17-13 shows the velocity measurement timing
diagram.
QEIM<2:0>
Velocity Event Mode
001
010
x2 Velocity Event mode. The velocity
pulse is generated on every QEA edge.
101
110
x4 Velocity Event mode. The velocity
pulse is generated on every QEA and
QEB active edge.
FIGURE 17-12:
VELOCITY MEASUREMENT BLOCK DIAGRAM
TMR5 Reset
Reset
Logic
QEI
Control
Logic
Clock
TMR5
16
TCY
Velocity Mode
Velocity Capture
IC1
Velocity Event
Postscaler
(VELR Register)
CAP3/QEB
QEB
QEA
INDX
Direction
Clock
CAP2/QEA
CAP1/INDX
Position
Counter
2010 Microchip Technology Inc.
DS39616D-page 167
MICROCHIP [ MICROCHIP ]
