PIC18F2331/2431/4331/4431
FIGURE 17-9:
QEI INPUTS WHEN SAMPLED BY THE FILTER (DIVIDE RATIO = 1:1)
TCY
QEA Pin
(1)
TQEI = 16 TCY
QEB Pin
QEA Input
TGD = 3 TCY
QEB Input
Note 1: The module design allows a quadrature frequency of up to FQEI = FCY/16.
FIGURE 17-10:
QEI MODULE RESET TIMING ON PERIOD MATCH
Forward
Reverse
QEA
QEB
+1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
Count (+/-)
(1)
POSCNT
MAXCNT
IC2QEIF
MAXCNT=1527
Note 6
Note 2
Note 2
UP/DOWN
(3)
(3)
Q4
Q4
(5)
(4)
Q1
Q1
Position
Counter Load
IC3DRIF
(5)
Q1
Note 1: The POSCNT register is shown in QEI x4 Update mode (POSCNT increments on every rising and every falling edge
of QEA and QEB input signals). Asynchronous external QEA and QEB inputs are synchronized to the TCY clock by
the input sampling FF in the noise filter (see Figure 17-14).
2: When POSCNT = MAXCNT, POSCNT is reset to ‘0’ on the next QEA rising edge. POSCNT is set to MAXCNT when
POSCNT = 0(when decrementing), which occurs on the next QEA falling edge.
3: IC2QEIF is generated on the Q4 rising edge.
4: Position counter is loaded with ‘0’ (which is a rollover event in this case) on POSCNT = MAXCNT.
5: Position counter is loaded with MAXCNT value (1527h) on underflow.
6: IC2QEIF must be cleared in software.
2010 Microchip Technology Inc.
DS39616D-page 165
MICROCHIP [ MICROCHIP ]
