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PIC18F4431-I/P 参数 Datasheet PDF下载

PIC18F4431-I/P图片预览
型号: PIC18F4431-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术,高性能PWM和A / D [28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D]
分类和应用: 闪存微控制器
文件页数/大小: 392 页 / 3127 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2331/2431/4331/4431  
TABLE 11-7: PORTD I/O SUMMARY  
TRIS  
Setting  
I/O  
Pin  
Function  
I/O  
Description  
Type  
RD0/T0CKI/  
T5CKI  
RD0  
0
1
1
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
O
I
DIG  
ST  
LATD<0> data output.  
PORTD<0> data input.  
(1)  
T0CKI  
I
ST  
Timer0 alternate clock input.  
Timer5 alternate clock input.  
LATD<1> data output.  
(1)  
T5CKI  
I
ST  
RD1/SDO  
RD1  
O
I
DIG  
ST  
PORTD<1> data input.  
(1)  
SDO  
O
O
I
DIG  
DIG  
ST  
SPI data out; takes priority over port data.  
LATD<2> data output.  
RD2/SDI/SDA  
RD2  
PORTD<2> data input.  
(1)  
SDI  
I
ST  
SPI data input (SSP module).  
(1)  
2
SDA  
O
I
DIG  
I C™ data output (SSP module); takes priority over port data.  
2
2
I C  
I C data input (SSP module).  
RD3/SCK/SCL  
RD3  
O
I
DIG  
ST  
LATD<3> data output.  
PORTD<3> data input.  
(1)  
SCK  
O
I
DIG  
ST  
SPI clock output (SSP module); takes priority over port data.  
SPI clock input (SSP module).  
(1)  
2
SCL  
O
I
DIG  
I C clock output (SSP module); takes priority over port data.  
2
2
I C  
I C clock input (SSP module); input type depends on module setting.  
RD4/FLTA  
RD4  
O
I
DIG  
ST  
LATD<4> data output.  
PORTD<4> data input.  
(2)  
FLTA  
I
ST  
Fault Interrupt Input Pin A.  
LATD<5> data output.  
RD5/PWM4  
RD6/PWM6  
RD7/PWM7  
RD5  
O
I
DIG  
ST  
PORTD<5> data input.  
(3)  
PWM4  
O
O
I
DIG  
DIG  
ST  
PWM Output 4; takes priority over port data.  
LATD<6> data output.  
RD6  
PORTD<6> data input.  
PWM6  
RD7  
O
O
I
DIG  
DIG  
ST  
PWM Output 6; takes priority over port data.  
LATD<7> data output.  
PORTD<7> data input.  
PWM7  
O
DIG  
PWM Output 7; takes priority over port data.  
Legend:  
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer;  
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).  
Note 1: RC3 is the alternate pin for T0CKI/T5CKI; RC4 is the alternate pin for SDI/SDA; RC5 is the alternate pin for SCK/SCL;  
RC7 is the alternate pin for SDO.  
2: RC1 is the alternate pin for FLTA.  
3: RB5 is the alternate pin for PWM4.  
TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD  
Reset Values  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
on Page:  
PORTD  
LATD  
RD7  
RD6  
RD5  
RD4  
RD3  
RD2  
RD1  
RD0  
57  
57  
57  
LATD Data Output Register  
TRISD  
PORTD Data Direction Register  
2010 Microchip Technology Inc.  
DS39616D-page 123  
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