PIC18FXX20
TABLE 3-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2)
Wake-up from
Oscillator
Brown-out
SLEEP or
Configuration
PWRTE = 0
PWRTE = 1
Oscillator Switch
HS with PLL enabled(1)
72 ms + 1024 TOSC
+ 2ms
1024 TOSC
+ 2 ms
72 ms(2) + 1024 TOSC
+ 2 ms
1024 TOSC + 2 ms
HS, XT, LP
EC
External RC
72 ms + 1024 TOSC
72 ms
1024 TOSC
1.5 µs
—
72 ms(2) + 1024 TOSC
1024 TOSC
1.5 µs(3)
—
72 ms(2)
72 ms
72 ms(2)
Note 1: 2 ms is the nominal time required for the 4xPLL to lock.
2: 72 ms is the nominal power-up timer delay, if implemented.
3: 1.5 µs is the recovery time from SLEEP. There is no recovery time from oscillator switch.
REGISTER 3-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R/W-1
TO
R/W-1
PD
R/W-1
POR
R/W-1
BOR
bit 7
Note 1: Refer to Section 4.14 (page 60) for bit definitions.
bit 0
TABLE 3-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Condition
RI TO PD POR BOR STKFUL STKUNF
Register
Power-on Reset
MCLR Reset during normal
operation
0000h
0000h
0--1 1100
1
u
1
u
1
u
0
u
0
u
u
u
u
u
0--u uuuu
Software Reset during normal
operation
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
0000h
0000h
0000h
0--0 uuuu
0--u uu11
0--u uu11
0
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
1
u
1
u
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
0000h
0000h
0--u 10uu
0--u 01uu
u--u 00uu
0--1 11u0
u--u 00uu
u
1
u
1
u
1
0
0
1
1
0
1
0
1
0
u
u
u
1
u
u
u
u
0
u
u
u
u
u
u
u
u
u
u
u
PC + 2
0000h
PC + 2(1)
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 31
MICROCHIP [ MICROCHIP ]
