PIC18FXX20
TABLE 3-3:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Applicable Devices
RESET Instruction
Stack Resets
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
IPR1
PIR1
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
0111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx(5)
--11 1111
--00 0000
--00 0000
-1-1 1111
-0-0 0000
-0-0 0000
0111 1111
0000 0000
0000 0000
0-00 --00
1111 1111
1111 1111
---1 1111
1111 1111
0000 -111
1111 1111
1111 1111
1111 1111
-111 1111(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
--uu uuuu
--uu uuuu
--uu uuuu
-u-u uuuu
-u-u uuuu(1)
-u-u uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu
u-uu --uu
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
uuuu uuuu
uuuu uuuu
---u uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
-uuu uuuu(5)
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIE1
MEMCON
TRISJ
TRISH
TRISG
TRISF
TRISE
TRISD
TRISC
TRISB
TRISA(5,6)
LATJ
LATH
LATG
LATF
LATE
LATD
LATC
LATB
LATA(5,6)
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 35
MICROCHIP [ MICROCHIP ]
