PIC18FXX20
If the main oscillator is configured for HS-PLL mode, an
oscillator start-up time (TOST), plus an additional PLL
time-out (TPLL), will occur. The PLL time-out is typically
2 ms and allows the PLL to lock to the main oscillator
frequency. A timing diagram, indicating the transition
from the Timer1 oscillator to the main oscillator for
HS-PLL mode, is shown in Figure 2-10.
FIGURE 2-10:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
TT1P
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q4
Q1
T1OSI
OSC1
TOST
TPLL
OSC2
TSCS
4
TOSC
PLL Clock
Input
1
2
3
5
6
7
8
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC
PC + 2
PC + 4
Note 1: TOST = 1024 TOSC (drawing not to scale).
If the main oscillator is configured in the RC, RCIO, EC
or ECIO modes, there is no oscillator start-up time-out.
Operation will resume after eight cycles of the main
oscillator have been counted. A timing diagram, indi-
cating the transition from the Timer1 oscillator to the
main oscillator for RC, RCIO, EC and ECIO modes, is
shown in Figure 2-11.
FIGURE 2-11:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
TT1P
T1OSI
OSC1
TOSC
6
1
4
5
7
8
2
3
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
TSCS
Program
Counter
PC
PC + 2
PC + 4
Note 1: RC Oscillator mode assumed.
2003 Microchip Technology Inc.
Advance Information
DS39609A-page 27
MICROCHIP [ MICROCHIP ]
