PIC18FXX20
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RESET Instruction
Stack Resets
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0--- -000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
xx-0 x000
---- ----
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0--- -000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 ----
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
---- --00
0000 0000
0000 0000
uu-0 u000
---- ----
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u--- -uuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
uu-0 u000
---- ----
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP1CON PIC18F6X20 PIC18F8X20
CCPR2H
CCPR2L
CCP2CON PIC18F6X20 PIC18F8X20
CCPR3H
CCPR3L
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
CCP3CON PIC18F6X20 PIC18F8X20
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
SPBRG1
RCREG1
TXREG1
TXSTA1
RCSTA1
EEADRH
EEADR
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
EEDATA
EECON2
EECON1
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609A-page 34
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
