PIC18FXX20
TABLE 3-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR Resets
WDT Reset
Power-on Reset,
Brown-out Reset
Wake-up via WDT
or Interrupt
Register
Applicable Devices
RESET Instruction
Stack Resets
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
1100 0000
N/A
TOSU
TOSH
TOSL
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
1111 1111
1100 0000
N/A
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
---u uuuu
uuuu uuuu
PC + 2(2)
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(1)
uuuu uuuu(1)
uuuu uuuu(1)
N/A
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0 PIC18F6X20 PIC18F8X20
POSTDEC0 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
N/A
N/A
---- xxxx
xxxx xxxx
xxxx xxxx
N/A
N/A
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
N/A
N/A
---- uuuu
uuuu uuuu
uuuu uuuu
N/A
POSTINC1 PIC18F6X20 PIC18F8X20
POSTDEC1 PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
PREINC1
PLUSW1
PIC18F6X20 PIC18F8X20
PIC18F6X20 PIC18F8X20
N/A
N/A
N/A
N/A
N/A
N/A
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as '0', q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ‘0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ‘0’.
DS39609A-page 32
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
