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PIC18LF6620-I/PT 参数 Datasheet PDF下载

PIC18LF6620-I/PT图片预览
型号: PIC18LF6620-I/PT
PDF下载: 下载PDF文件 查看货源
内容描述: 八十〇分之六十四引脚高性能1 Mbit的增强型闪存微控制器与A / D [64/80-Pin High Performance 1 Mbit Enhanced FLASH Microcontrollers with A/D]
分类和应用: 闪存微控制器和处理器外围集成电路PC时钟
文件页数/大小: 366 页 / 6797 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18FXX20  
The value in the ADRESH/ADRESL registers is not  
The following steps should be followed to do an A/D  
conversion:  
1. Configure the A/D module:  
modified  
for  
a
Power-on  
Reset.  
The  
ADRESH/ADRESL registers will contain unknown data  
after a Power-on Reset.  
• Configure analog pins, voltage reference and  
digital I/O (ADCON1)  
• Select A/D input channel (ADCON0)  
• Select A/D conversion clock (ADCON2)  
• Turn on A/D module (ADCON0)  
After the A/D module has been configured as desired,  
the selected channel must be acquired before the con-  
version is started. The analog input channels must  
have their corresponding TRIS bits selected as an  
input. To determine acquisition time, see Section 19.1.  
After this acquisition time has elapsed, the A/D  
conversion can be started.  
2. Configure A/D interrupt (if desired):  
• Clear ADIF bit  
• Set ADIE bit  
• Set GIE bit  
3. Wait the required acquisition time.  
4. Start conversion:  
• Set GO/DONE bit (ADCON0 register)  
5. Wait for A/D conversion to complete, by either:  
• Polling for the GO/DONE bit to be cleared  
OR  
• Waiting for the A/D interrupt  
6. Read A/D Result registers (ADRESH:ADRESL);  
clear bit ADIF, if required.  
7. For next conversion, go to step 1 or step 2, as  
required. The A/D conversion time per bit is  
defined as TAD. A minimum wait of 2 TAD is  
required before next acquisition starts.  
FIGURE 19-2:  
ANALOG INPUT MODEL  
VDD  
Sampling  
Switch  
VT = 0.6V  
ANx  
SS  
RIC 1k  
RSS  
Rs  
CPIN  
5 pF  
I leakage  
± 500 nA  
VAIN  
CHOLD = 120 pF  
VT = 0.6V  
VSS  
Legend: CPIN  
VT  
= input capacitance  
= threshold voltage  
6V  
5V  
I LEAKAGE = leakage current at the pin due to  
VDD 4V  
3V  
various junctions  
= interconnect resistance  
= sampling switch  
RIC  
SS  
2V  
CHOLD  
RSS  
= sample/hold capacitance (from DAC)  
= sampling switch resistance  
5
6
7
8 9 10 11  
Sampling Switch ( k)  
2003 Microchip Technology Inc.  
Advance Information  
DS39609A-page 217  
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