PIC18FXX20
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(VDD and VSS), or the voltage level on the
RA3/AN3/VREF+ pin and RA2/AN2/VREF- pin.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off and
any conversion is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input (RA3 can also be a volt-
age reference), or as a digital I/O. The ADRESH and
ADRESL registers contain the result of the A/D conver-
sion. When the A/D conversion is complete, the result
is loaded into the ADRESH/ADRESL registers, the
GO/DONE bit (ADCON0 register) is cleared, and A/D
interrupt flag bit, ADIF, is set. The block diagram of the
A/D module is shown in Figure 19-1.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 19-1:
A/D BLOCK DIAGRAM
CHS3:CHS0
1111
AN15(1)
1110
AN14(1)
1101
AN13(1)
1100
AN12(1)
1011
AN11
1010
AN10
1001
AN9
1000
AN8
0111
AN7
0110
AN6
0101
AN5
0100
AN4
VAIN
(Input Voltage)
0011
10-bit
AN3
Converter
A/D
0010
AN2
0001
VCFG1:VCFG0
AN1
0000
AN0
VDD
VREF+
VREF-
Reference
Voltage
VSS
Note 1: Channels AN15 through AN12 are not available on PIC18F6X20 devices.
2: I/O pins have diode protection to VDD and VSS.
DS39609A-page 216
Advance Information
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
