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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
If INDF0, INDF1 or INDF2 are read indirectly via an  
5.12 Indirect Addressing, INDF and  
FSR Registers  
FSR, all ‘0’s are read (zero bit is set). Similarly, if  
INDF0, INDF1 or INDF2 are written to indirectly, the  
operation will be equivalent to a NOPinstruction and the  
status bits are not affected.  
Indirect addressing is a mode of addressing data mem-  
ory, where the data memory address in the instruction  
is not fixed. An FSR register is used as a pointer to the  
data memory location that is to be read or written. Since  
this pointer is in RAM, the contents can be modified by  
the program. This can be useful for data tables in the  
data memory and for software stacks. Figure 5-8  
shows how the fetched instruction is modified prior to  
being executed.  
5.12.1  
INDIRECT ADDRESSING  
OPERATION  
Each FSR register has an INDF register associated  
with it, plus four additional register addresses. Perform-  
ing an operation using one of these five registers  
determines how the FSR will be modified during  
indirect addressing.  
Indirect addressing is possible by using one of the  
INDF registers. Any instruction using the INDF register  
actually accesses the register pointed to by the File  
Select Register, FSR. Reading the INDF register itself,  
indirectly (FSR = 0), will read 00h. Writing to the INDF  
register indirectly, results in a no operation. The FSR  
register contains a 12-bit address which is shown in  
Figure 5-9.  
When data access is performed using one of the five  
INDFn locations, the address selected will configure  
the FSRn register to:  
• Do nothing to FSRn after an indirect access (no  
change) – INDFn  
• Auto-decrement FSRn after an indirect access  
(post-decrement) – POSTDECn  
The INDFn register is not a physical register. Address-  
ing INDFn actually addresses the register whose  
address is contained in the FSRn register (FSRn is a  
pointer); this is indirect addressing.  
• Auto-increment FSRn after an indirect access  
(post-increment) – POSTINCn  
• Auto-increment FSRn before an indirect access  
(pre-increment) – PREINCn  
Example 5-5 shows a simple use of indirect addressing  
to clear the RAM in Bank 1 (locations 100h-1FFh) in a  
minimum number of instructions.  
• Use the value in the WREG register as an offset  
to FSRn. Do not modify the value of the WREG or  
the FSRn register after an indirect access (no  
change) – PLUSWn  
EXAMPLE 5-5:  
HOW TO CLEAR RAM  
(BANK 1) USING  
When using the auto-increment or auto-decrement  
features, the effect on the FSR is not reflected in the  
Status register. For example, if the indirect address  
causes the FSR to equal ‘0’, the Z bit will not be set.  
INDIRECT ADDRESSING  
LFSR FSR0,0x100 ;  
NEXT  
CLRF POSTINC0  
; Clear INDF  
; register then  
; inc pointer  
; All done with  
; Bank1?  
; NO, clear next  
; YES, continue  
Auto-incrementing or auto-decrementing an FSR  
affects all 12 bits. That is, when FSRnL overflows from  
an increment, FSRnH will be incremented  
automatically.  
BTFSS FSR0H, 1  
GOTO NEXT  
CONTINUE  
Adding these features allows the FSRn to be used as a  
stack pointer, in addition to its use for table operations  
in data memory.  
There are three indirect addressing registers. To  
address the entire data memory space (4096 bytes),  
these registers are 12 bits wide. To store the 12 bits of  
addressing information, two 8-bit registers are  
required:  
Each FSR has an address associated with it that per-  
forms an indexed indirect access. When a data access  
to this INDFn location (PLUSWn) occurs, the FSRn is  
configured to add the signed value in the WREG regis-  
ter and the value in FSR to form the address before an  
indirect access. The FSR value is not changed. The  
WREG offset range is -128 to +127.  
1. FSR0: composed of FSR0H:FSR0L  
2. FSR1: composed of FSR1H:FSR1L  
3. FSR2: composed of FSR2H:FSR2L  
If an FSR register contains a value that points to one of  
the INDFn, an indirect read will read 00h (zero bit is set)  
while an indirect write will be equivalent to a NOP  
(status bits are not affected).  
In addition, there are registers INDF0, INDF1 and  
INDF2, which are not physically implemented. Reading  
or writing to these registers activates indirect address-  
ing with the value in the corresponding FSR register  
being the address of the data. If an instruction writes a  
value to INDF0, the value will be written to the address  
pointed to by FSR0H:FSR0L. A read from INDF1 reads  
the data from the address pointed to by  
FSR1H:FSR1L. INDFn can be used in code anywhere  
an operand can be used.  
If an indirect addressing write is performed when the  
target address is an FSRnH or FSRnL register, the  
data is written to the FSR register but no pre- or  
post-increment/decrement is performed.  
DS39599C-page 66  
2003 Microchip Technology Inc.  
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