PIC18F2220/2320/4220/4320
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the Status register
5.13 Status Register
The Status register, shown in Register 5-2, contains the
arithmetic status of the ALU. The Status register can be
the operand for any instruction as with any other regis-
ter. If the Status register is the destination for an instruc-
tion that affects the Z, DC, C, OV or N bits, then the
write to these five bits is disabled. These bits are set or
cleared according to the device logic. Therefore, the
result of an instruction with the Status register as
destination may be different than intended.
as 000u u1uu(where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF and MOVWF instructions are used to
alter the Status register, because these instructions do
not affect the Z, C, DC, OV or N bits in the Status reg-
ister. For other instructions not affecting any status bits,
see Table 24-2.
Note:
The C and DC bits operate as a borrow
and digit borrow bit respectively, in
subtraction.
REGISTER 5-2:
STATUS REGISTER
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
OV
R/W-x
Z
R/W-x
DC
R/W-x
C
N
bit 7
bit 0
bit 7-5
bit 4
Unimplemented: Read as ‘0’
N: Negative bit
This bit is used for signed arithmetic (2’s complement). It indicates whether the result was
negative (ALU MSB = 1).
1= Result was negative
0= Result was positive
bit 3
OV: Overflow bit
This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit
magnitude which causes the sign bit (bit 7) to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 2
bit 1
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions.
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the bit 4 or bit 3 of the source register.
bit 0
C: Carry/borrow bit
For ADDWF, ADDLW, SUBLWand SUBWFinstructions.
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note:
For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS39599C-page 68
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
