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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
TABLE 5-2:  
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)  
Value on  
POR, BOR  
Details on  
page:  
File Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
OSCCON  
LVDCON  
WDTCON  
IDLEN  
IRCF2  
IRCF1  
IRVST  
IRCF0  
LVDEN  
OSTS  
LVDL3  
IOFS  
LVDL2  
SCS1  
LVDL1  
SCS0  
LVDL0  
0000 q000  
--00 0101  
--- ---0  
26, 47  
47, 233  
47, 246  
SWDTEN  
RCON  
IPEN  
RI  
TO  
PD  
POR  
BOR  
0--1 11q0 45, 69, 98  
TMR1H  
TMR1L  
T1CON  
TMR2  
Timer1 Register High Byte  
Timer1 Register Low Byte  
xxxx xxxx  
xxxx xxxx  
0000 0000  
0000 0000  
1111 1111  
47, 125  
47, 125  
47, 121  
47, 127  
47, 127  
47, 127  
RD16  
T1RUN  
T1CKPS1  
T1CKPS0 T1OSCEN  
T1SYNC  
TMR2ON  
TMR1CS  
T2CKPS1  
TMR1ON  
Timer2 Register  
PR2  
Timer2 Period Register  
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0  
SSP Receive Buffer/Transmit Register  
T2CON  
SSPBUF  
T2CKPS0 -000 0000  
xxxx xxxx  
47, 156,  
164  
SSPADD  
SSPSTAT  
SSP Address Register in I2C Slave mode. SSP Baud Rate Reload Register in I2C Master mode.  
0000 0000  
47, 164  
SMP  
WCOL  
GCEN  
CKE  
D/A  
P
S
R/W  
SSPM2  
PEN  
UA  
BF  
0000 0000  
47, 156,  
165  
SSPCON1  
SSPOV  
SSPEN  
CKP  
SSPM3  
RCEN  
SSPM1  
RSEN  
SSPM0  
SEN  
0000 0000  
47, 157,  
166  
SSPCON2  
ADRESH  
ADRESL  
ADCON0  
ADCON1  
ADCON2  
CCPR1H  
CCPR1L  
CCP1CON  
ACKSTAT  
ACKDT  
ACKEN  
0000 0000  
xxxx xxxx  
xxxx xxxx  
--00 0000  
--00 0000  
0-00 0000  
xxxx xxxx  
xxxx xxxx  
0000 0000  
47, 167  
48, 220  
48, 220  
48, 211  
48, 212  
48, 213  
48, 134  
48, 134  
A/D Result Register High Byte  
A/D Result Register Low Byte  
CHS3  
VCFG1  
ACQT2  
CHS2  
VCFG0  
ACQT1  
CHS1  
PCFG3  
ACQT0  
CHS0  
PCFG2  
ADCS2  
GO/DONE  
PCFG1  
ADON  
PCFG0  
ADCS0  
ADFM  
ADCS1  
Capture/Compare/PWM Register 1 High Byte  
Capture/Compare/PWM Register 1 Low Byte  
P1M1(5)  
P1M0(5)  
DC1B1  
DC1B0  
CCP1M3  
CCP1M2  
CCP1M1  
CCP1M0  
48, 133,  
141  
CCPR2H  
CCPR2L  
CCP2CON  
PWM1CON(5)  
ECCPAS(5)  
CVRCON  
CMCON  
TMR3H  
Capture/Compare/PWM Register 2 High Byte  
Capture/Compare/PWM Register 2 Low Byte  
xxxx xxxx  
xxxx xxxx  
--00 0000  
0000 0000  
0000 0000  
000- 0000  
0000 0111  
xxxx xxxx  
xxxx xxxx  
0000 0000  
0000 0000  
0000 0000  
48, 134  
48, 134  
48, 133  
48, 149  
48, 150  
48, 227  
48, 221  
48, 131  
48, 131  
48, 129  
48, 198  
DC2B1  
PDC5  
DC2B0  
PDC4  
CCP2M3  
PDC3  
CCP2M2  
PDC2  
CCP2M1  
PDC1  
CCP2M0  
PDC0  
PRSEN  
PDC6  
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0  
PSSAC1  
CVR3  
PSSAC0  
CVR2  
PSSBD1  
CVR1  
PSSBD0  
CVR0  
CVREN  
C2OUT  
CVROE  
C1OUT  
CVRR  
C2INV  
C1INV  
CIS  
CM2  
CM1  
CM0  
Timer3 Register High Byte  
Timer3 Register Low Byte  
TMR3L  
T3CON  
RD16  
T3CCP2  
T3CKPS1  
T3CKPS0  
T3CCP1  
T3SYNC  
TMR3CS  
TMR3ON  
SPBRG  
USART Baud Rate Generator  
USART Receive Register  
RCREG  
48, 204,  
203  
TXREG  
USART Transmit Register  
0000 0000  
48, 202,  
203  
TXSTA  
RCSTA  
CSRC  
SPEN  
TX9  
RX9  
TXEN  
SREN  
SYNC  
CREN  
BRGH  
FERR  
TRMT  
OERR  
TX9D  
RX9D  
0000 -010  
0000 000x  
48, 196  
48, 197  
ADDEN  
Legend:  
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition  
Note 1:  
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read  
0’ in all other oscillator modes.  
2:  
3:  
4:  
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.  
Bit 21 of the PC is only available in Test mode and Serial Programming modes.  
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as  
analog input and read ‘0’ following a Reset.  
5:  
6:  
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.  
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is  
read-only.  
2003 Microchip Technology Inc.  
DS39599C-page 63  
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