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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
TABLE 5-2:  
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320) (CONTINUED)  
Value on  
POR, BOR  
Details on  
page:  
File Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
EEADR  
EEDATA  
EECON2  
EECON1  
IPR2  
EEPROM Address Register  
EEPROM Data Register  
0000 0000  
0000 0000  
48, 81  
48, 84  
EEPROM Control Register 2 (not a physical register)  
0000 0000 48, 72, 81  
xx-0 x000 48, 73, 82  
EEPGD  
OSCFIP  
OSCFIF  
OSCFIE  
PSPIP(5)  
PSPIF(5)  
PSPIE(5)  
CFGS  
CMIP  
CMIF  
CMIE  
ADIP  
ADIF  
ADIE  
FREE  
EEIP  
WRERR  
BCLIP  
BCLIF  
BCLIE  
SSPIP  
SSPIF  
SSPIE  
TUN3  
WREN  
LVDIP  
WR  
RD  
TMR3IP  
TMR3IF  
TMR3IE  
TMR2IP  
TMR2IF  
TMR2IE  
TUN1  
CCP2IP  
CCP2IF  
CCP2IE  
TMR1IP  
TMR1IF  
TMR1IE  
TUN0  
11-1 1111  
00-0 0000  
00-0 0000  
1111 1111  
0000 0000  
0000 0000  
--00 0000  
0000 -111  
1111 1111  
1111 1111  
1111 1111  
1111 1111  
---- -xxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
---- xxxx  
49, 97  
49, 93  
PIR2  
EEIF  
LVDIF  
PIE2  
EEIE  
LVDIE  
49, 95  
IPR1  
RCIP  
RCIF  
RCIE  
TUN5  
IBOV  
TXIP  
CCP1IP  
CCP1IF  
CCP1IE  
TUN2  
49, 96  
PIR1  
TXIF  
49, 92  
PIE1  
TXIE  
49, 94  
OSCTUNE  
TRISE(5)  
TRISD(5)  
TRISC  
TRISB  
TRISA  
LATE(5)  
LATD(5)  
LATC  
TUN4  
PSPMODE  
23, 49  
IBF  
OBF  
Data Direction bits for PORTE(5)  
49, 112  
49, 110  
49, 108  
49, 106  
49, 103  
49, 113  
49, 110  
49, 108  
49, 106  
49, 103  
49, 113  
Data Direction Control Register for PORTD  
Data Direction Control Register for PORTC  
Data Direction Control Register for PORTB  
TRISA7(2)  
TRISA6(1) Data Direction Control Register for PORTA  
Read/Write PORTE Data Latch  
Read/Write PORTD Data Latch  
Read/Write PORTC Data Latch  
Read/Write PORTB Data Latch  
LATB  
LATA  
LATA<7>(2) LATA<6>(1) Read/Write PORTA Data Latch  
RE3(6)  
PORTE  
Read PORTE pins,  
Write PORTE Data Latch(5)  
PORTD  
PORTC  
PORTB  
PORTA  
Read PORTD pins, Write PORTD Data Latch  
Read PORTC pins, Write PORTC Data Latch  
Read PORTB pins, Write PORTB Data Latch(4)  
RA7(2) RA6(1)  
Read PORTA pins, Write PORTA Data Latch  
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xx0x 0000  
49, 110  
49, 108  
49, 106  
49, 103  
Legend:  
Note 1:  
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read  
0’ in all other oscillator modes.  
2:  
3:  
4:  
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.  
Bit 21 of the PC is only available in Test mode and Serial Programming modes.  
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as  
analog input and read ‘0’ following a Reset.  
5:  
6:  
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.  
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is  
read-only.  
DS39599C-page 64  
2003 Microchip Technology Inc.  
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