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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
TABLE 5-2:  
File Name  
TOSU  
REGISTER FILE SUMMARY (PIC18F2220/2320/4220/4320)  
Value on  
POR, BOR  
Details on  
page:  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Top-of-Stack Upper Byte (TOS<20:16>)  
---0 0000  
0000 0000  
0000 0000  
00-0 0000  
---0 0000  
0000 0000  
0000 0000  
--00 0000  
0000 0000  
0000 0000  
0000 0000  
xxxx xxxx  
xxxx xxxx  
0000 000x  
1111 -1-1  
11-0 0-00  
n/a  
46, 54  
46, 54  
46, 54  
46, 55  
46, 56  
46, 56  
46, 56  
46, 74  
46, 74  
46, 74  
46, 74  
46, 85  
46, 85  
46, 89  
46, 90  
46, 91  
46, 66  
46, 66  
46, 66  
46, 66  
46, 66  
46, 66  
46, 66  
46  
TOSH  
Top-of-Stack High Byte (TOS<15:8>)  
Top-of-Stack Low Byte (TOS<7:0>)  
TOSL  
STKPTR  
PCLATU  
PCLATH  
PCL  
STKFUL  
STKUNF  
bit 21(3)  
Return Stack Pointer  
Holding Register for PC<20:16>  
Holding Register for PC<15:8>  
PC Low Byte (PC<7:0>)  
TBLPTRU  
TBLPTRH  
TBLPTRL  
TABLAT  
PRODH  
PRODL  
INTCON  
INTCON2  
INTCON3  
INDF0  
bit 21  
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)  
Program Memory Table Pointer High Byte (TBLPTR<15:8>)  
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)  
Program Memory Table Latch  
Product Register High Byte  
Product Register Low Byte  
GIE/GIEH PEIE/GIEL  
TMR0IE  
INTEDG1  
INT0IE  
INTEDG2  
INT2IE  
RBIE  
TMR0IF  
TMR0IP  
INT0IF  
RBIF  
RBIP  
RBPU  
INTEDG0  
INT1IP  
INT2IP  
INT1IE  
INT2IF  
INT1IF  
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)  
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)  
POSTINC0  
n/a  
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)  
n/a  
PREINC0  
PLUSW0  
FSR0H  
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)  
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)  
n/a  
n/a  
Indirect Data Memory Address Pointer 0 High  
---- 0000  
xxxx xxxx  
xxxx xxxx  
n/a  
FSR0L  
Indirect Data Memory Address Pointer 0 Low Byte  
Working Register  
WREG  
INDF1  
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)  
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)  
46, 66  
46, 66  
46, 66  
46, 66  
46, 66  
47, 66  
47, 66  
47, 65  
47, 66  
47, 66  
47, 66  
47, 66  
47, 66  
47, 66  
47, 66  
47, 68  
47, 119  
47, 119  
47, 117  
POSTINC1  
n/a  
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)  
n/a  
PREINC1  
PLUSW1  
FSR1H  
FSR1L  
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)  
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)  
n/a  
n/a  
Indirect Data Memory Address Pointer 1 High  
---- 0000  
xxxx xxxx  
---- 0000  
n/a  
Indirect Data Memory Address Pointer 1 Low Byte  
BSR  
Bank Select Register  
INDF2  
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)  
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)  
POSTINC2  
n/a  
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)  
n/a  
PREINC2  
PLUSW2  
FSR2H  
FSR2L  
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)  
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)  
n/a  
n/a  
Indirect Data Memory Address Pointer 2 High  
---- 0000  
xxxx xxxx  
---x xxxx  
0000 0000  
xxxx xxxx  
1111 1111  
Indirect Data Memory Address Pointer 2 Low Byte  
STATUS  
TMR0H  
TMR0L  
T0CON  
N
OV  
Z
DC  
C
Timer0 Register High Byte  
Timer0 Register Low Byte  
TMR0ON  
T08BIT  
T0CS  
T0SE  
PSA  
T0PS2  
T0PS1  
T0PS0  
Legend:  
x= unknown, u= unchanged, - = unimplemented, q= value depends on condition  
Note 1:  
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator mode only and read  
0’ in all other oscillator modes.  
2:  
3:  
4:  
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.  
Bit 21 of the PC is only available in Test mode and Serial Programming modes.  
If PBADEN = 0, PORTB<4:0> are configured as digital input and read unknown and if PBADEN = 1, PORTB<4:0> are configured as  
analog input and read ‘0’ following a Reset.  
5:  
6:  
These registers and/or bits are not implemented on the PIC18F2X20 devices and read as ‘0’.  
The RE3 port bit is only available when MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’. Otherwise, RE3 reads ‘0’. This bit is  
read-only.  
DS39599C-page 62  
2003 Microchip Technology Inc.  
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