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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
TABLE 4-3:  
Register  
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)  
MCLR Resets  
WDT Reset  
Power-on Reset,  
Brown-out Reset  
Wake-up via WDT  
or Interrupt  
Applicable Devices  
RESET Instruction  
Stack Resets  
IPR2  
PIR2  
PIE2  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
11-1 1111  
00-0 0000  
00-0 0000  
1111 1111  
-111 1111  
0000 0000  
-000 0000  
0000 0000  
-000 0000  
--00 0000  
0000 -111  
1111 1111  
1111 1111  
1111 1111  
1111 1111(5)  
---- -xxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx(5)  
---- xxxx  
xxxx xxxx  
xxxx xxxx  
xxxx xxxx  
xx0x 0000(5)  
11-1 1111  
00-0 0000  
00-0 0000  
1111 1111  
-111 1111  
0000 0000  
-000 0000  
0000 0000  
-000 0000  
--00 0000  
0000 -111  
1111 1111  
1111 1111  
1111 1111  
1111 1111(5)  
---- -uuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu(5)  
---- xxxx  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uu0u 0000(5)  
uu-u uuuu  
uu-u uuuu(1)  
uu-u uuuu  
uuuu uuuu  
-uuu uuuu  
uuuu uuuu(1)  
-uuu uuuu(1)  
uuuu uuuu  
-uuu uuuu  
--uu uuuu  
uuuu -uuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu(5)  
---- -uuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu(5)  
---- uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu  
uuuu uuuu(5)  
IPR1  
PIR1  
PIE1  
OSCTUNE 2220 2320 4220 4320  
TRISE  
TRISD  
TRISC  
TRISB  
TRISA(5)  
LATE  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
2220 2320 4220 4320  
LATD  
LATC  
LATB  
LATA(5)  
PORTE  
PORTD  
PORTC  
PORTB  
PORTA(5)  
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.  
Shaded cells indicate conditions do not apply for the designated device.  
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).  
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the  
interrupt vector (0008h or 0018h).  
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are  
updated with the current value of the PC. The STKPTR is modified to point to the next location in the  
hardware stack.  
4: See Table 4-2 for Reset value for specific condition.  
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When  
not enabled as PORTA pins, they are disabled and read ‘0’.  
2003 Microchip Technology Inc.  
DS39599C-page 49