PIC18F2220/2320/4220/4320
TABLE 4-3:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
MCLR Resets
Power-on Reset,
Brown-out Reset
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Register
Applicable Devices
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
xxxx xxxx
xxxx xxxx
--00 0000
--00 0000
0-00 0000
xxxx xxxx
xxxx xxxx
0000 0000
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
000- 0000
0000 0111
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
xx-0 x000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
--00 0000
0-00 0000
uuuu uuuu
uuuu uuuu
0000 0000
--00 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 0000
0000 0000
000- 0000
0000 0111
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
0000 0000
0000 0000
uu-0 u000
0000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
--uu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuu- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-0 u000
0000 0000
CCP1CON
CCPR2H
CCPR2L
CCP2CON 2220 2320 4220 4320
PWM1CON 2220 2320 4220 4320
ECCPAS
CVRCON
CMCON
TMR3H
TMR3L
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
2220 2320 4220 4320
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON1
EECON2
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, q= value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the
interrupt vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-2 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
DS39599C-page 48
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
