PIC18F2220/2320/4220/4320
TABLE 4-1:
Oscillator
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out
Exit from
Configuration
Power Managed Mode
PWRTEN = 0
PWRTEN = 1
HSPLL
66 ms(1) + 1024 TOSC + 2 ms(2)
66 ms(1) + 1024 TOSC
66 ms(1)
1024 TOSC + 2 ms(2)
1024 TOSC + 2 ms(2)
HS, XT, LP
EC, ECIO
1024 TOSC
1024 TOSC
—
—
—
—
—
—
RC, RCIO
66 ms(1)
66 ms(1)
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
2: 2 ms is the nominal time required for the 4x PLL to lock.
REGISTER 4-1:
RCON REGISTER BITS AND POSITIONS
R/W-0
IPEN
U-0
—
U-0
—
R/W-1
RI
R-1
TO
R-1
PD
R/W-1
POR
R/W-1
BOR
bit 7
bit 0
Note:
Refer to Section 5.14 “RCON Register” for bit definitions.
TABLE 4-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Counter
RCON
Register
Condition
RI TO PD POR BOR STKFUL STKUNF
Power-on Reset
RESETInstruction
Brown-out
0000h
0000h
0000h
0--1 1100
0--0 uuuu
0--1 11u-
1
0
1
1
u
1
1
u
1
0
u
u
0
u
0
0
u
u
0
u
u
MCLR during power managed
Run modes
0000h
0000h
0000h
0--u 1uuu
0--u 10uu
0--u 0uuu
u
u
u
1
1
0
u
0
u
u
u
u
u
u
u
u
u
u
u
u
u
MCLR during power managed
Idle modes and Sleep mode
WDT Time-out during full power
or power managed Run mode
MCLR during full power
execution
u
1
u
u
u
1
Stack Full Reset (STVREN = 1)
0000h
0--u uuuu
u
u
u
u
u
Stack Underflow Reset
(STVREN = 1)
Stack Underflow Error (not an
actual Reset, STVREN = 0)
0000h
PC + 2
PC + 2
u--u uuuu
u--u 00uu
u--u u0uu
u
u
u
u
0
u
u
0
0
u
u
u
u
u
u
u
u
u
1
u
u
WDT Time-out during power
managed Idle or Sleep modes
Interrupt exit from power
managed modes
Legend: u= unchanged, x= unknown, - = unimplemented bit, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
2003 Microchip Technology Inc.
DS39599C-page 45
MICROCHIP [ MICROCHIP ]
