PIC18F2220/2320/4220/4320
4.0
RESET
The PIC18F2X20/4X20 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
Power-on Reset (POR)
MCLR Reset while executing instructions
MCLR Reset when not executing instructions
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET
Instruction
Stack Full Reset
Stack Underflow Reset
Most registers are not affected by a WDT wake-up
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
Reset situations as indicated in Table 4-2. These bits
are used in software to determine the nature of the
Reset. See Table 4-3 for a full description of the Reset
states of all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 4-1.
The enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses.
The MCLR pin is not driven low by any internal Resets,
including the WDT.
The MCLR input provided by the MCLR pin can be dis-
abled with the MCLRE bit in Configuration Register 3H
(CONFIG3H<7>). See
for more information.
Most registers are unaffected by a Reset. Their status
is unknown on POR and unchanged by all other
Resets. The other registers are forced to a “Reset
state” depending on the type of Reset that occurred.
FIGURE 4-1:
RESET
Instruction
Stack
Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset
MCLR
MCLRE
( )_IDLE
Sleep
WDT
Time-out
V
DD
Rise
Detect
V
DD
Brown-out
Reset
BOREN
OST/PWRT
1024 Cycles
OST
10-bit Ripple Counter
OSC1
32
µs
INTRC
(1)
POR Pulse
S
Chip_Reset
R
Q
PWRT
65.5 ms
11-bit Ripple Counter
Enable PWRT
Enable OST
(2)
Note 1:
This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
2:
See Table 4-1 for time-out situations.
2003 Microchip Technology Inc.
DS39599C-page 43
MICROCHIP [ MICROCHIP TECHNOLOGY ]
