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PIC18F2320-I/SP 参数 Datasheet PDF下载

PIC18F2320-I/SP图片预览
型号: PIC18F2320-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 28 /40/ 44引脚高性能,增强型闪存微控制器与10位A / D和纳瓦技术 [28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 388 页 / 6899 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC18F2220/2320/4220/4320  
17.3 SPI Mode  
17.0 MASTER SYNCHRONOUS  
SERIAL PORT (MSSP)  
MODULE  
The SPI mode allows 8 bits of data to be synchronously  
transmitted and received, simultaneously. All four  
modes of SPI are supported. To accomplish  
communication, typically three pins are used:  
17.1 Master SSP (MSSP) Module  
Overview  
• Serial Data Out (SDO) – RC5/SDO  
• Serial Data In (SDI) – RC4/SDI/SDA  
The Master Synchronous Serial Port (MSSP) module is  
a serial interface useful for communicating with other  
peripheral or microcontroller devices. These peripheral  
devices may be serial EEPROMs, shift registers, dis-  
play drivers, A/D converters, etc. The MSSP module  
can operate in one of two modes:  
• Serial Clock (SCK) – RC3/SCK/SCL  
Additionally, a fourth pin may be used when in a Slave  
mode of operation:  
• Slave Select (SS) – RA5/AN4/SS/LVDIN/C2OUT  
Register 17-1 shows the block diagram of the MSSP  
module when operating in SPI mode.  
• Serial Peripheral Interface (SPI)  
• Inter-Integrated Circuit (I2C)  
- Full Master mode  
FIGURE 17-1:  
MSSP BLOCK DIAGRAM  
(SPI MODE)  
- Slave mode (with general address call)  
The I2C interface supports the following modes in  
hardware:  
Internal  
Data Bus  
Read  
Write  
• Master mode  
• Multi-Master mode  
• Slave mode  
SSPBUF reg  
SSPSR reg  
17.2 Control Registers  
The MSSP module has three associated registers.  
These include a status register (SSPSTAT) and two  
control registers (SSPCON1 and SSPCON2). The use  
of these registers and their individual configuration bits  
differ significantly, depending on whether the MSSP  
module is operated in SPI or I2C mode.  
RC4/SDI/SDA  
RC5/SDO  
Shift  
Clock  
bit 0  
Control  
Enable  
SS  
Additional details are provided under the individual  
sections.  
RA5/AN4/SS/  
LVDIN/C2OUT  
Edge  
Select  
2
Clock Select  
SSPM3:SSPM0  
SMP:CKE  
2
4
TMR2 Output  
(
)
2
Edge  
Select  
TOSC  
Prescaler  
4, 16, 64  
RC3/SCK/  
SCL  
Data to TX/RX in SSPSR  
TRIS bit  
2003 Microchip Technology Inc.  
DS39599C-page 155  
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