PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RA5/TX/CK
pin
121
121
RA4/RX/DT
pin
120
122
TABLE 17-9: SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
—
—
65
35
ns
ns
121
122
TckRF
TdtRF
Clock out rise time and fall time (Master
Mode)
10
Data out rise time and fall time
—
10
35
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RA5/TX/CK
125
pin
RA4/RX/DT
pin
126
TABLE 17-10: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
15
—
—
ns
Data hold before CK↓ (DT hold time)
126
TckL2dtl
Data hold after CK↓ (DT hold time)
15
—
—
ns
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30412C-page 160
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
