PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 17-12: MEMORY INTERFACE READ TIMING
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
166
ALE
OE
164
168
160
165
Data in
161
AD<15:0>
WR
Addr out
Addr out
150
162
151
163
167
'1'
'1'
TABLE 17-12: MEMORY INTERFACE READ REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
150
TadV2alL
TalL2adI
TadZ2oeL
AD<15:0> (address) valid to ALE↓
(address setup time)
0.25Tcy - 30
5*
—
—
—
—
ns
ns
151
ALE↓ to address out invalid
(address hold time)
160
161
162
AD<15:0> high impedance to OE↓
0*
0.25Tcy - 15
35
—
—
—
—
—
—
ns
ns
ns
ToeH2adD OE↑ to AD<15:0> driven
TadV2oeH Data in valid before OE↑
(data setup time)
163
164
ToeH2adI
TalH
OE↑to data in invalid (data hold time)
0
—
—
—
ns
ns
ALE pulse width
—
0.25TCY §
165
166
167
ToeL
OE pulse width
0.5Tcy - 35 §
—
TCY §
—
—
—
ns
ns
ns
TalH2alH
Tacc
ALE↑ to ALE↑ (cycle time)
Address access time
—
—
0.75 TCY-40
0.5 TCY - 60
168
Toe
Output enable access time
(OE low to Data Valid)
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification guaranteed by design.
DS30412C-page 162
1996 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
