PIC17C75X
FIGURE 12-5: TMR0 READ/WRITE IN TIMER MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
AD15:AD0
ALE
WR_TRM0L
WR_TMR0H
RD_TMR0L
12
AB
12
13
56
TMR0H
57
58
TMR0L
FE
FF
MOVFP
MOVFP
MOVPF
MOVPF
TMR0L,W
MOVPF
MOVPF
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Instruction
fetched
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L Read TMR0L
Previously
Fetched
Instruction
MOVFP
MOVFP
MOVPF
MOVPF
MOVPF
Instruction
executed
DATAL,TMR0L DATAH,TMR0H
TMR0L,W
TMR0L,W
TMR0L,W
Write TMR0L Write TMR0H Read TMR0L Read TMR0L Read TMR0L
In this example, old TMR0 value is 12FEh, new value of AB56h is written.
TABLE 12-1: REGISTERS/BITS ASSOCIATED WITH TIMER0
Value on
POR,
BOR
Value on all
other resets
(Note1)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h, Unbanked
06h, Unbanked
07h, Unbanked
0Bh, Unbanked
0Ch, Unbanked
T0STA
INTEDG
—
T0SE
—
T0CS
STKAV
T0IF
T0PS3
GLINTD
INTF
T0PS2
TO
T0PS1
PD
T0PS0
POR
—
0000 000-
--11 1100
0000 0000
xxxx xxxx
xxxx xxxx
0000 000-
--11 qq11
0000 0000
uuuu uuuu
uuuu uuuu
CPUSTA
INTSTA
TMR0L
TMR0H
BOR
INTE
PEIF
T0CKIF
PEIE
T0CKIE
T0IE
TMR0 register; low byte
TMR0 register; high byte
Legend:
Note 1:
x= unknown, u= unchanged, -= unimplemented read as a '0', q- value depends on condition, Shaded cells are not used by Timer0.
Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
DS30264A-page 90
Preliminary
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
