PIC17C75X
TABLE 18-2: PIC17CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
f,d
f,d
f,d
f,s
f,d
f
ADD WREG to f
1
1
1
1
1
0000 111d ffff ffff
0001 000d ffff ffff
0000 101d ffff ffff
0010 100s ffff ffff
0001 001d ffff ffff
OV,C,DC,Z
ADD WREG and Carry bit to f
AND WREG with f
OV,C,DC,Z
Z
None
Z
Clear f, or Clear f and Clear WREG
Complement f
3
COMF
CPFSEQ
CPFSGT
CPFSLT
DAW
Compare f with WREG, skip if f = WREG
Compare f with WREG, skip if f > WREG
Compare f with WREG, skip if f < WREG
Decimal Adjust WREG Register
Decrement f
1 (2) 0011 0001 ffff ffff
1 (2) 0011 0010 ffff ffff
1 (2) 0011 0000 ffff ffff
None 6,8
f
None 2,6,8
None 2,6,8
f
f,s
f,d
f,d
f,d
f,d
f,d
f,d
f,d
f,p
p,f
f
1
1
0010 111s ffff ffff
0000 011d ffff ffff
C
3
DECF
OV,C,DC,Z
DECFSZ
DCFSNZ
INCF
Decrement f, skip if 0
Decrement f, skip if not 0
Increment f
1 (2) 0001 011d ffff ffff
1 (2) 0010 011d ffff ffff
None 6,8
None 6,8
1
0001 010d ffff ffff
OV,C,DC,Z
INCFSZ
INFSNZ
IORWF
MOVFP
MOVPF
MOVWF
MULWF
NEGW
Increment f, skip if 0
Increment f, skip if not 0
Inclusive OR WREG with f
Move f to p
1 (2) 0001 111d ffff ffff
1 (2) 0010 010d ffff ffff
None 6,8
None 6,8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000 100d ffff ffff
011p pppp ffff ffff
010p pppp ffff ffff
0000 0001 ffff ffff
0011 0100 ffff ffff
0010 110s ffff ffff
0000 0000 0000 0000
0001 101d ffff ffff
0010 001d ffff ffff
0001 100d ffff ffff
0010 000d ffff ffff
0010 101s ffff ffff
0000 010d ffff ffff
0000 001d ffff ffff
0001 110d ffff ffff
Z
None
Move p to f
Z
Move WREG to f
None
f
Multiply WREG with f
Negate WREG
None
f,s
—
f,d
f,d
f,d
f,d
f,s
f,d
f,d
f,d
OV,C,DC,Z 1,3
NOP
No Operation
None
C
RLCF
Rotate left f through Carry
Rotate left f (no carry)
Rotate right f through Carry
Rotate right f (no carry)
Set f
RLNCF
RRCF
None
C
RRNCF
SETF
None
None
OV,C,DC,Z
OV,C,DC,Z
None
3
1
1
SUBWF
SUBWFB
SWAPF
TABLRD
TABLWT
Subtract WREG from f
Subtract WREG from f with Borrow
Swap f
t,i,f Table Read
t,i,f Table Write
2 (3) 1010 10ti ffff ffff
1010 11ti ffff ffff
None
7
5
2
None
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Work-
ing register (WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkkis loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
DS30264A-page 186
1997 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
