PIC17C75X
TABLE 18-2: PIC17CXXX INSTRUCTION SET (Cont.’d)
Mnemonic,
Operands
Description
Cycles
16-bit Opcode
Status
Affected
Notes
MSb
LSb
TLRD
t,f
t,f
f
Table Latch Read
Table Latch Write
Test f, skip if 0
1
1
1010 00tx ffff ffff
1010 01tx ffff ffff
None
None
TLWT
TSTFSZ
XORWF
1 (2) 0011 0011 ffff ffff
None 6,8
Z
f,d
Exclusive OR WREG with f
1
0000 110d ffff ffff
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f,b
f,b
f,b
f,b
f,b
Bit Clear f
1
1
1000 1bbb ffff ffff
1000 0bbb ffff ffff
None
BSF
Bit Set f
None
BTFSC
BTFSS
BTG
Bit test, skip if clear
Bit test, skip if set
Bit Toggle f
1 (2) 1001 1bbb ffff ffff
1 (2) 1001 0bbb ffff ffff
None 6,8
None 6,8
None
1
0011 1bbb ffff ffff
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
ADD literal to WREG
1
1
2
1
2
1
2
1
1
1
1
2
2
2
1
1
1
1011 0001 kkkk kkkk
1011 0101 kkkk kkkk
111k kkkk kkkk kkkk
0000 0000 0000 0100
110k kkkk kkkk kkkk
1011 0011 kkkk kkkk
1011 0111 kkkk kkkk
1011 1000 uuuu kkkk
1011 101x kkkk uuuu
1011 0000 kkkk kkkk
1011 1100 kkkk kkkk
0000 0000 0000 0101
1011 0110 kkkk kkkk
0000 0000 0000 0010
0000 0000 0000 0011
1011 0010 kkkk kkkk
1011 0100 kkkk kkkk
OV,C,DC,Z
k
AND literal with WREG
Subroutine Call
Z
None
TO,PD
None
Z
k
7
7
CLRWDT
GOTO
—
k
Clear Watchdog Timer
Unconditional Branch
IORLW
LCALL
MOVLB
MOVLR
MOVLW
MULLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
Inclusive OR literal with WREG
Long Call
k
None 4,7
None
k
Move literal to low nibble in BSR
Move literal to high nibble in BSR
Move literal to WREG
k
None
k
None
k
Multiply literal with WREG
Return from interrupt (and enable interrupts)
Return literal to WREG
Return from subroutine
Enter SLEEP Mode
None
—
k
GLINTD
7
7
7
None
None
—
—
k
TO, PD
OV,C,DC,Z
Z
Subtract WREG from literal
Exclusive OR literal with WREG
k
Legend: Refer to Table 18-1 for opcode field descriptions.
Note 1: 2’s Complement method.
2: Unsigned arithmetic.
3: If s = '1', only the file is affected: If s = '0', both the WREG register and the file are affected; If only the Work-
ing register (WREG) is required to be affected, then f = WREG must be specified.
4: During an LCALL, the contents of PCLATH are loaded into the MSB of the PC and kkkk kkkkis loaded into
the LSB of the PC (PCL)
5: Multiple cycle instruction for EPROM programming when table pointer selects internal EPROM. The instruc-
tion is terminated by an interrupt event. When writing to external program memory, it is a two-cycle instruc-
tion.
6: Two-cycle instruction when condition is true, else single cycle instruction.
7: Two-cycle instruction except for TABLRDto PCL (program counter low byte) in which case it takes 3 cycles.
8: A “skip” means that instruction fetched during execution of current instruction is not executed, instead an
NOP is executed.
1997 Microchip Technology Inc.
DS30264A-page 187
MICROCHIP [ MICROCHIP ]
