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PIC17C752T-25I/P 参数 Datasheet PDF下载

PIC17C752T-25I/P图片预览
型号: PIC17C752T-25I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS微控制器的EPROM [High-Performance 8-Bit CMOS EPROM Microcontrollers]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 320 页 / 2172 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C75X  
15.2.14.1 BUS COLLISION DURING A START  
CONDITION  
If the SDA pin is sampled low during this count, the  
BRG is reset and the SDA line is asserted early  
(Figure 15-40). If however a '1' is sampled on the SDA  
pin, the SDA pin is asserted low at the end of the BRG  
count. The baud rate generator is then reloaded and  
counts down to 0, and during this time, if the SCL pins  
is sampled as '0', a bus collision does not occur. At  
the end of the BRG count the SCL pin is asserted low.  
During a START condition, a bus collision occurs if:  
a) SDA or SCL are sampled low at the beginning of  
the START condition (Figure 15-38)  
b) SCL is sampled low before SDA is asserted low.  
(Figure 15-39)  
During a START condition both the SDA and the SCL  
pins are monitored.  
Note: The reason that bus collision is not a factor  
during a START condition is that no two  
bus masters can assert a START condition  
at the exact same time. Therefore, one  
master will always assert SDA before the  
other. This condition does not cause a bus  
collision because the two masters must be  
allowed to arbitrate the first address follow-  
ing the START condition, and if the  
address is the same, arbitration must be  
allowed to continue into the data portion,  
RESTART, or STOP conditions.  
If:  
the SDA pin is already low  
or the SCL pin is already low,  
then:  
the START condition is aborted,  
and the BCLIF flag is set,  
and the SSP module is reset to its IDLE state  
(Figure 15-38).  
The START condition begins with the SDA and SCL  
pins de-asserted. When the SDA pin is sampled high,  
the baud rate generator is loaded from SSPADD<6:0>  
and counts down to 0. If the SCL pin is sampled low  
while SDA is high, a bus collision occurs, because it is  
assumed that another master is attempting to drive a  
data '1' during the START condition.  
FIGURE 15-38: BUS COLLISION DURING START CONDITION (SDA ONLY)  
SDA goes low before the SEN bit is set.  
. Set BCLIF,  
S bit and SSPIF set because  
SDA = 0, SCL = 1  
SDA  
SCL  
Set SEN, enable start  
condition if SDA = 1, SCL=1  
SEN cleared automatically because of bus collision.  
SSP module reset into idle state.  
SEN  
SDA sampled low before  
START condition.  
Set BCLIF.  
S bit and SSPIF set because  
SDA = 0, SCL = 1  
BCLIF  
SSPIF and BCLIF are  
cleared in software.  
S
SSPIF  
SSPIF and BCLIF are  
cleared in software.  
1997 Microchip Technology Inc.  
Preliminary  
DS30264A-page 161  
 
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