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PIC17C752T-25I/P 参数 Datasheet PDF下载

PIC17C752T-25I/P图片预览
型号: PIC17C752T-25I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能8位CMOS微控制器的EPROM [High-Performance 8-Bit CMOS EPROM Microcontrollers]
分类和应用: 微控制器可编程只读存储器电动程控只读存储器
文件页数/大小: 320 页 / 2172 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC17C75X  
15.2.14 MULTI -MASTER COMMUNICATION, BUS  
COLLISION, AND BUS ARBITRATION  
If a START, RESTART, STOP, or Acknowledge condi-  
tion was in progress when the bus collision occurred,  
the condition is aborted, the SDA and SCL lines are  
de-asserted, and the respective control bits in the  
SSPCON2 register are cleared. When the user ser-  
vices the bus collision interrupt service routine, and if  
the I2C bus is free, the user can resume communica-  
tion by asserting a START condition.  
Multi-Master mode support is achieved by bus arbitra-  
tion. When the master outputs address/data bits onto  
the SDA pin, arbitration takes place when the master  
outputs a '1' on SDA by letting SDA float high and  
another master asserts a '0'. When the SCL pin floats  
high, data should be stable. If the expected data on  
SDA is a '1' and the data sampled on the SDA pin = '0',  
then a bus collision has taken place. The master will  
set the Bus Collision Interrupt Flag, BCLIF and reset  
The Master will continue to monitor the SDA and SCL  
pins, and if a STOP condition occurs, the SSPIF bit will  
be set.  
2
the I C port to its IDLE state. (Figure 15-37).  
A write to the SSPBUF will start the transmission of  
data at the first data bit, regardless of where the trans-  
mitter left off when bus collision occurred.  
If a transmit was in progress when the bus collision  
occurred, the transmission is halted, the BF flag is  
cleared, the SDA and SCL lines are de-asserted, and  
the SSPBUF can be written to. When the user ser-  
vices the bus collision interrupt service routine, and if  
In multi-master mode, the interrupt generation on the  
detection of start and stop conditions allows the deter-  
2
mination of when the bus is free. Control of the I C  
2
the I C bus is free, the user can resume communica-  
bus can be taken when the P bit is set in the SSPSTAT  
register, or the bus is idle and the S and P bits are  
cleared.  
tion by asserting a START condition.  
FIGURE 15-37: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE  
Sample SDA. While SCL is high  
data doesn’t match what is driven  
by the master.  
SDA line pulled low  
by another source  
Data changes  
while SCL = 0  
Bus collision has occurred.  
SDA released  
by master  
SDA  
SCL  
Set bus collision  
interrupt.  
BCLIF  
DS30264A-page 160  
Preliminary  
1997 Microchip Technology Inc.  
 
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